The present invention relates to a microprogram control (to be referred to as "MC" hereunder) apparatus for controlling the sequence of elementary operations within an information handling system.
Such an MC apparatus for higher speed processing has been proposed in the U.S. Pat. No. 3,800,293. The proposed apparatus is equipped with first and second control stores 18 and 19 as shown in the drawing each of which stores a plurality of microinstructions for carrying out a system instruction of higher order. With this apparatus, the final microinstruction (MI-instruction) of the plurality of MI-instructions stored in the first control store (CS) 18 is executed concurrently and in parallel with the execution of the initial MI-instruction of the plural MI-instructions stored in the second CS 19. However, the other MI-instructions stored in the two CSs 18 and 19 are performed serially. In this way, since the final MI-instruction of the first system instruction and the first MI-instruction of the second system instruction are executed in parallel, the total execution time required can be comparatively reduced as compared with the sequential processing of such MI-instruction sequences, without stopping the operation of an arithmetic unit.
However, an increased number of MI-instructions for controlling complicated processing causes an increase in the capacity of each of the used CSs, which in turn results in an increase in the memory access time for each of the CSs, disturbing the high-speed operation.